The present invention relates to a thin-film-transistor (TFT) for a semiconductor memory device and the fabricating method thereof, and more particularly to a PMOS TFT transistor of an SRAM with a 6-transistor memory cell configuration and the fabricating method thereof.
Recently, utilizing dynamic random access devices (DRAM) mass production lines, the makers of semiconductor memory devices have strived to increase the production of static random access memories (SRAMs) because of the increasing demand for SRAMs and the unstable price of DRAMs. The increase in the demand for SRAMs is because they have unique characteristics such as high speed, low power consumption, no refresh requirements and a simplified system design, and due to the trend toward multifunctional, high-quality, miniaturized and lightweight systems. However, since SRAMs have a more complicated cell structure than DRAMs, the density of the SRAMs is behind by one generation.
Current SRAMs are divided into 4-transistor and 6-transistor cell configurations. The 4-transistor type leads with respect to capacity, employing a memory cell of NMOS form having a polysilicon as a high resistance load and periphery circuits of CMOS form. Due to chip size, 256 Kb SRAMs are produced primarily, disregarding low power consumption SRAMs having full CMOS configuration. Therefore, recently, a stack-type TFT changing the high resistance polysilicon load into one for PMOS, is adopted to reduce the power consumption and maintain a chip size similar to that of the conventional 4-transistor type ("Symposium on VLSI Technology," 1990, pp. 19-24).
However, source, drain and channel regions of a conventional TFT are arranged in a two-dimensional plane structure to occupy large areas. Accordingly, the TFT in a two-dimensional structure impedes the high density and large capacity of an SRAM.